a language differs from either a conventional programing language therein the execution of program statements is non strictly linear. The Verilog model consists of the hierarchy of modules. Modules come defined using the placed of input, output, & bidirectional ports. Internally, the module contains the listings of wires & registers. Cooccurring & serial statements define a behaviour of a module by defining a relationships between the ports, wires, & registers. Sequent statements come positioned around a begin/end prevent & executed in serial choose in the prevent. However wholly coincident statements & 100% beginside/end obstructs in the project come executed in parallel. The module can too contain 1 or even other cases of an additional module to define sub-behavior.

The subset of the statements in the language is synthesizable. Whenever the modules in a project contain lone synthesizable statements, a project may typically become transformed into the circuit layout of a computer chip utilizing appropriate software program.

History
Beginning
Verilog was number 1 developed at Gateway Design Automation around 1984 as a hardware modeling language. Gateway Project Automation was late purchased by Cadence Design Systems in 1990. Cadence at present got fully proprietary rights to Gateway's Verilog & a Verilog-XL simulator logic simulators.

Standard Opened
By having a increasing profits of VHDL, Cadence moved down the Open Standards route. Cadence transferred Verilog into a public domain under a [http://www.ovi.org Open Verilog International] (OVI) (today referred to as Accellera) organization. Verilog was late submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to handle a deficiencies that users experienced noticed in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog 2001

Superlog/System Verilog
A advent of High Level Verification languages like OpenVera, & Verisity's E language encouraged the development of Superlog by Co-Design Automation Inc. Co-Project Automation Inc was late purchased by Synopsys. A foundations of Superlog & Vera keep around been donated to Accellera. It has been transformed & updated to SystemVerilog which will belike be a next IEEE standard.

A latest versions of the language include trend lines for parallel & mixed signal modelling. Which are actually known as [http://www.verilog-ams.com Verilog-AMS].

Example
The elementary lesson of ii flip-flops follows:

module toplevel(clock,reset);

    reg flop1;
    reg flop2;

    universally @ (posedge reset or even posedge clock) 
    // non sure as shooting however shouldn't ton this text exist as this statement here to produce this function?: in case (reset)
    begin
        flop1 <= 0;
        flop2 <= 1;
    end
    else
    begin
        flop1 <= flop2;
        flop2 <= flop1;
    end
endmodule

The "<=" operator in verilog is another aspect of its being a hardware description language as opposed to a normal procedural language. This is known as a "non-blocking" assignment. When the simulation runs, all of the signals assigned with a "<=" operator have their assignment scheduled until after all statements occurring during the same point in time have executed. After all the statements have been executed for one event, the scheduled assignments are performed. This makes it easier to code behaviours that happen simultaneously.

In the above example, flop1 is assigned flop2, and flop2 is assigned flop1. These statements are executed during the same time event. Since the assignments are coded with the "<=" non-blocking operator, the assignments are scheduled to occur at the end of the event. Until then, all reads to flop1 and flop2 will use the values they had at the beginning of the time event.

This means that the order of the assignments are irrelevant and will produce the same result. flop1 and flop2 will swap values every clock.

The other choice for assignment is an "=" operator and this is known as a blocking assignment. When the "=" operator is used, things occur in the sequence they occur much like a procedural language.

In the above example, if the statements had used the "=" blocking operator instead, then the order of the statements would affect the behaviour. If the same code were used but changed to "=" operators, the reset would set flop2 to a 1, and flop1 to a 0. A clock event would set flop1 to flop2 (a 1) and this assignment would happen immediately. The next statement would assign flop2 to flop1, which is now a 1. Rather than swap values every clock, flop1 and flop2 would both become 1 and remain that way.

An example counter circuit follows:

module Div20x (rst, clk, cet, cep, count,tc);
//TITLE   'Divide-by-20 Counter with enables'

//enable CEP is a clock enable only
//enable CET is a clock enable and enables the TC output

//a counter using the Verilog language

    parameter size = 5;
    parameter length = 20;

    input rst;  // These inputs/outputs represent connections to
    input clk;  // the module.  
    input cet;
    input cep;

    output [size-1:0] count; 
    output tc;

    reg [size-1:0] count;  // Signals assigned within an always (or initial) block
                           // must be of type reg
    wire tc;               // Other signals are of type wire
    
    // The always statement below is a parallel execution statement that
    // executes any time the signals rst or clk transition from low to high
    always @ (posedge rst or posedge clk) 
                 
       if (rst)             // This simulates a reset of the counter                   
           count <= 5'b0;
       else 
       if (cet && cep) // This simulates the enables both being true
         begin
           if (count == length-1)
              count <= 5'b0;
           else
              count <= count + 5'b1;  // 5'b1 is 5 bits wide and 
         end                          // equal to the value 1.


    // the value of tc is continuously assigned the value of the expression
    assign tc = (cet && (count == length-1));

endmodule

Example:
...
reg a, b, c, d;
wire e;
...
always @(b or e)
  begin
     a = b & e;
     b = a | b;
     #5 c = b;
     d = #6 c ^ e;
  end

The always clause above illustrates the other type of method of use, i.e. the always clause executes any time any of the entities in the list change, i.e. the b or e change. When one of these changes, immediately a and b are assigned new values. After a delay of 5 time units, c is assigned the value of b and the value of c ^ e is tucked away in an invisible store. Then after 6 more time units, d is assigned the value that was tucked away.

Signals that are driven from within a process (an initial or always block) must be of type reg. Signals that are driven from outside a process must be of type wire. The keyword reg does not necessarily infer a hardware register.

Synthesizeable Constructs

As mentioned previously, there are several basic templates that can be used to represent hardware.

// Mux examples
// The first example uses continuous assignment

wire wire_out ;

assign  wire_out = sel ? a : b;

// the second example uses a procedure to accomplish
// the same thing. 

reg reg_out;
always @(a or b or sel)
  reg_out = sel ? a: b;

// Finally - you can use if/else in a procedural structure.
reg if_out;
always @(a or b or sel)
  if (sel)
       if_out = a;
  else
       if_out = b;

The next interesting structure is a latch. A latch operates differently from a register. A latch will pass the input to the output when the gate signal is one state, while it was capture the input and store it at the transition of the gate signal. The output will remain stable while the input can transition when the gate signals the storage state.

// Latch example

reg latch_out;
always @(gate or din)
  if(gate)
      latch_out = din;  // Pass through state
                        // Note that the else isn't required
                        // here. The variable will follow
                        // the value of din while the signal
                        // gate is high. when gate goes low,
                        // latch_out will remain constant.
                       

The flip/flop is the next significant template. The basic D flop can be modeled as found below:

reg q;
always @(posedge clk)
  q <= d;

The significant thing to notice in the D flop example is the first use of the non-blocking assignment. A basic rule of thumb is to use <= when there is a posedge or negedge statement within the always clause.

The next variant of the D flop is one with an asynchronous reset. There is a convention that the reset state will be the first if clause within the statement.

reg q;
always @(posedge clk or posedge reset)
  if(reset == 1)
    q <= 0;
  else
    q <= d;

The next variant is a flop including both an asynchronous reset and asynchronous set condition. Again the convention comes into play, i.e. the reset term is followed by the set term.

reg q;
always @(posedge clk or posedge reset or posedge set)
  if(reset == 1)
    q <= 0;
  else
  if(set == 1)
    q <= 1;
  else
    q <= d;

The final basic variant of the flop is one that implements a flop with a mux feeding its input. The mux has a d input and feedback from the flop itself. This allows a gated load function.

// Basic structure with feedback path illustrated
always @(posedge clk)
  if(gate)
    q <= d;
  else
    q <= q;

// The more common structure ASSUMES the feedback is present
// This is a safe assumption since this is how the
// hardware compiler will interpret it.  This structure
// looks much like a Latch. The differences are the
// @(posedge clk) and the non-blocking <=
// 
always @(posedge clk)
  if(gate)
    q <= din;  // the mux is "implied"

Looking at the original counter example you can see a combination of the basic asynchronous reset flop and Gated input flop used. The register variable count is set to zero on the rising edge or rst. When rst is 0, the variable count will load new data when cet && cep is true.

System Tasks

System tasks are available to handle simple I/O, and various design measurement functions. You'll note that all the system tasks start with a $. This section presents a short list of the most often used tasks. It is by no means a comprehensive list.

• $display - Print a line followed by an automatic newline.
• $write - Print a line without the newline.
• $readmemh - Read hex file content into a memory array.
• $readmemb - Read binary file content into a memory array.
• $monitor - Print out all the listed variables when any change value.
• $time - Value of current simulation time.
• $dumpfile - Declare the VCD ( Value Change Dump ) format output file name.
• $dumpvars - Turn on and dump the variables.
• $random - Return a random value.

See Also
VHDL SystemC HardwareC